1. Field of the Invention
The present invention pertains to stacked devices of semiconductor integrated circuits (ICs), and more particularly relates to stacked devices such as three-dimensional (3D) integrated circuits in which semiconductor chips are stacked and the like, and a method of manufacturing the stacked devices.
2. Description of the Related Art
The integration degree of semiconductor integrated circuits continues to be promoted with the advance of a microprocessing technology. However, it is supposed that a limit of miniaturization will come in the finer and finer advance of the microprocessing technology. In association with the difficulty in the advance of the microprocessing technology, attention is paid to a 3D integrated circuit in which IC chips are stacked. Among the techniques for achieving the 3D integrated circuit, a technique for vertically stacking a plurality of IC chips, in each of the IC chips minute elements are delineated at chip level, is expected. However, when the upper level IC chip is stacked on the lower level IC chip, the upper and lower level IC chips are required to be precisely position-aligned. Thus, a throughput can not be made so high. Moreover, even if the upper and lower level IC chips are mechanically positioned, the alignment accuracy between the upper and lower level IC chips is about one micrometer at most. Hence, an alignment accuracy between the upper and lower level IC chips can not be made so high.
In view of such circumstances, a method of manufacturing a 3D integrated circuit is proposed. The proposed method includes a step of coating liquid on a plurality of temporally to-be-jointed areas, which are defined in a transfer-substrate respectively, so as to form a plurality of droplets of the liquid; a step of floating a plurality of IC chips on the plurality of droplets, which are separated for each of temporally to-be-jointed areas, and using the surface tension of the liquid, position-aligning each of the chips in each of the temporally to-be-jointed areas; and a step of vaporizing the droplets of the liquid, which are inserted between each of the IC chips and the temporally to-be-jointed areas, respectively, and temporally jointing each of the IC chips to the temporally to-be-jointed areas (please see JP 2010-225803A).
However, the above self-aligning method based on the surface tension of the liquid only, which is described in JP 2010-225803A, has a limit in the accuracy of alignment. Moreover, the self-aligning method has a problem such that a jointing process, after the upper level IC chip is stacked on the lower level IC chip, is complex and difficult.
Therefore, an object of the present invention is to provide a stacked device in which it is possible to easily achieve a high precision position-alignment with 0.2 micrometer accuracy or less, which extremely exceeds a precision of the self-alignment based on the surface tension of the liquid only, and it is simple to carry out the jointing process after the stacking process of the chips, and a method of manufacturing the stacked devices.